This invention relates to a frequency counter for counting pulses of a variable input signal using another input signal of a different fixed frequency as a reference. Such frequency counters are commonly used to measure the frequency of signals and in some cases the noise characteristics of RF (Radio Frequency) sources.
A conventional frequency counter consists of a signal gate followed by a counter. The signal gate is caused to open for a known period of time, which is usually a predetermined number of cycles of a stable reference frequency. The counter counts the number of input cycles that occur during this gate time, this count being representative o the ratio of the input signal frequency to the reference frequency.
The performance of such a conventional counter will now be discussed with reference to FIG. 1 of the accompanying drawings, which shows a train I of input signal pulses and, on the same time axis, the gate signal G. If the gate time was an integral number of input periods long, as is shown in FIG. 1, then the leading and trailing edges of the gate pulse would be equally spaced from the respective next succeeding input pulses, i.e. the intervals ta and tb would be equal. The count would then represent exactly the ratio of the input frequency to the gate frequency. In general, however, this is not the case and the gate signal and input signal are uncorrelated. The difference between the actual gate time, and the gate time that would return an exact frequency count is ta-tb. As both ta and tb can vary from zero to one input period, the total error on the gate time will vary over +/-1 input period. The fractional error introduced into the count by this uncertainty is (ta-tb) divided by the gate time. This result is equivalent to the more common statement that the error of a counter is +/- one count, or +/- the gate frequency. As the error is dependent on the gate time used, the design of a conventional counter involves a trade-off between speed and resolution.
There are three main ways, known in the art, of improving this trade-off, i.e. of reducing the fractional uncertainty without increasing the reading time.
The first two of these ways make use of the fact that the uncertainty in the gate time is proportional to the period of the counted signal. Both ways involve putting a frequency higher than the input frequency into an otherwise conventional counter.
According to the first way, the frequency of the counted input signal is raised by using a high frequency VCO (voltage controlled oscillator), locked through a fixed divider to the input signal in a phase locked loop arrangement. The magnitude of the error falls directly as a function of the multiplication factor of the loop. This method is only useful when the input frequency is sufficiently low to be cheaply and conveniently multiplied in this way.
The second way is useful whenever the input frequency is lower than the reference frequency. The gate signal is derived from the input signal instead of the reference signal, and the reference frequency (higher than the input frequency) is counted. Since a counter only compares the ratio of two frequencies, it does not matter which frequency is counted and which is used to derive the gate. Although the reading from the counter now represents the period rather than the frequency of the input signal, a reciprocal conversion is trivial for any processor-based instrument.
The third way of improving the trade-off between speed and resolution is more recent than the first two: the error on the gate time is reduced by measuring the actual time delays, i.e. ta and tb, between the edges of the gate signal and the input signal, using fast timing circuits.
The purpose of the present invention is to control the time error involved in the necessary synchronisation of the input and reference signals rather than to estimate or to ignore the time error.